In an I/O input receiver on a semiconductor integrated circuit, in order to make it possible to receive an external minute amplitude, a current-mirror differential amplifier is used in many cases. Although the differential amplifier is generally used to compare two signals with each other, there are two cases, i.e., a case where differential signals are compared with each other, and case where an input signal of a system is compared with fixed potential.
In the case where the differential signals are compared with each other, comparison of equal signals is carried out, and hence the characteristics of the circuit become better, and the performance is improved. However, two external interconnects are required for a one bit input signal, and hence disadvantages such as an increase in the number of interconnects, increase in the power consumption, and the like are increased.
On the other hand, in the case where the input signal of a system is compared with the fixed potential, common fixed potential can be shared by a plurality of I/Os, and hence there is an advantage that the number of interconnects can be small, and disadvantage that the circuit performance is reduced because of the asymmetry of the signals.
An input receiver in which a current-mirror differential amplifier is used is generally constituted of a current-mirror differential amplifier, and inverter in the subsequent stage is configured to carry out waveform shaping of an output of the current-mirror differential amplifier. The current-mirror differential amplifier includes a pair of first and second PMOS transistors constituting a current mirror circuit, a pair of first and second NMOS transistors each of which is connected to each of the first and second PMOS transistors in series, and which constitute a differential pair circuit, and NMOS transistor TNCS used for a constant current source. Fixed potential reference potential) VREF which is an external input signal is input to a gate terminal of the first NMOS transistor TNA1, and an input signal IN that is an external input signal is input to a gate terminal of the second NMOS transistor TNA2. An output signal OUTn of the current-mirror differential amplifier is output from a signal output node which is a common connection node of a drain terminal of the second PMOS transistor TPM2 and a drain terminal of the second NMOS transistor TNA2.
In the conventional circuit having the configuration described above, when the external input signal IN rises from “L” to “H”, the potential of the node of the output signal OUTn is quickly discharged through the second NMOS transistor TNA2, and hence the potential of the output signal OUTn quickly lowers to “L”.
However, when the external input signal IN falls from “H” to “L”, an operation in which the potential of the common connection node of a gate terminal of the first PMOS transistor TPM1, and gate terminal of the second PMOS transistor TPM2 is lowered through the first NMOS transistor TNA1, the current flowing through the second PMOS transistor TPM2 increases, and a node of the output signal OUTn is charged is carried out, and hence a signal transition speed of the output signal OUTn at the time at which the signal OUTn rises to “H” becomes lower than when the potential of the output signal OUTn lowers to “L”.
As described above, in the conventional input receiver in which the current-mirror differential amplifier is used, a transition time difference of the output signal occurs between the rise time and fall time of the input signal. As a result of this, in a circuit in which a signal received by an input receiver is used, it is necessary to carry out setup/hold in accordance with the timing of later transition time, and hence there is the problem that a margin of the setup/hold lowers.
It should be noted that in Jpn. Pat. Appln. KOKAI Publication No. 2005-130332, a differential amplifier configured to output a maximum of four multivalued voltage levels for two input voltages is disclosed.